1. Field of the Invention
The invention relates to the field of physical circuit design and, more particularly, to packing and clustering components of a circuit design.
2. Description of the Related Art
Circuit designs, and particularly designs for Field Programmable Gate Arrays (FPGA's), have become increasingly complex and heterogeneous. Modern circuit designs can include a variety of different components or resources including, but not limited to, registers, block Random Access Memory (RAM), multipliers, processors, and the like. This increasing complexity makes placement and signal routing of circuit designs more cumbersome.
Circuit packing provides a degree of simplification. Circuit packing refers to the grouping or association of circuit components into larger clusters of components. For a given design, a packer “packs” circuit components together based on particular objective functions. Each clustered grouping of components then can be treated as a single, larger component for purposes of circuit placement and signal routing. The packing process effectively reduces the number of components to be processed during subsequent circuit design tasks.
Packing refers to both mandatory packing as well as non-mandatory packing. Mandatory packing refers to packing operations that are performed as dictated by the circuit architecture. For example, mandatory packing can include packing objects so as to implement carry chains, block random access memory (RAM), or other circuit structures. In contrast, non-mandatory packing refers to the packing of objects for purposes that are unrelated to the underlying circuit architecture. For example, non-mandatory packing can include packing components to achieve a particular signal propagation delay based upon topological circuit information.
Packing typically occurs prior to the placement and routing tasks of physical circuit design. Accordingly, as noted, the packing task serves to simplify circuit design as once components are clustered together as a single, larger circuit component, the placing and routing tasks effectively are left with fewer components to process. Unfortunately, the tradeoff for this simplification is reduced granularity. In other words, while having fewer components to place and route simplifies circuit design, the reduced granularity affords fewer choices with respect to circuit placement and routing.
What is needed is a technique which provides the benefits of circuit packing while not restricting granularity or the choices available to subsequent circuit design tasks.